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LTC6994-1/LTC6994-2 TimerBlox: Delay Block/ Debouncer FEATURES
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DESCRIPTION
The LTC(R)6994 is a programmable delay block with a range of 1s to 33.6 seconds. The LTC6994 is part of the TimerBloxTM family of versatile silicon timing devices. A single resistor, RSET , programs an internal master oscillator frequency, setting the LTC6994's time base. The input-to-output delay is determined by this master oscillator and an internal clock divider, NDIV , programmable to eight settings from 1 to 221: tDELAY = NDIV *RSET * 1s, NDIV = 1, 8, 64,...,221 50k
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Delay Range: 1s to 33.6 Seconds Configured with 1 to 3 Resistors Delay Max Error: - <2.3% for Delay > 512s - <3.4% for Delay of 8s to 512s - <5.1% for Delay of 1s to 8s Delay One or Both Rising/Falling Edges 2.25V to 5.5V Single Supply Operation 70A Supply Current at 10s Delay 500s Start-Up Time CMOS Output Driver Sources/Sinks 20mA -40C to 125C Operating Temperature Range Available in Low Profile (1mm) SOT-23 (ThinSOTTM) and 2mm x 3mm DFN
APPLICATIONS
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The output (OUT) follows the input (IN) after delaying the rising and/or falling transitions. The LTC6994-1 will delay the rising or falling edge. The LTC6994-2 will delay both transitions, and adds the option to invert the output.
DEVICE LTC6994-1 LTC6994-2 DELAY FUNCTION or or
Noise Discriminators/Pulse Qualifiers Delay Matching Switch Debouncing High Vibration, High Acceleration Environments Portable and Battery-Powered Equipment
L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks and TimerBlox and ThinSOT are trademarks of Linear Technology Corporation. All other trademarks are the property of their respective owners.
The LTC6994 also offers the ability to dynamically adjust the delay time via a separate control voltage. The LTC6994 is available in the 6-lead SOT-23 (ThinSOT) and 6-lead 2mm x 3mm DFN packages.
TYPICAL APPLICATION
Noise Discriminator
NOISY INPUT IN OUT LTC6994-2 GND V+ 0.1F RSET 75k SET DIV
699412 TA01a
QUALIFIED OUTPUT 3.3V
IN 2V/DIV 1.5s OUT 2V/DIV 20s/DIV
699412 TA01b
1.5s
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LTC6994-1/LTC6994-2 ABSOLUTE MAXIMUM RATINGS
(Note 1)
Supply Voltage (V+) to GND ........................................6V Maximum Voltage on Any Pin .................................. (GND - 0.3V) VPIN (V+ + 0.3V) Operating Temperature Range (Note 2) LTC6994C ............................................-40C to 85C LTC6994I .............................................-40C to 85C LTC6994H .......................................... -40C to 125C
Specified Temperature Range (Note 3) LTC6994C ................................................ 0C to 70C LTC6994I .............................................-40C to 85C LTC6994H .......................................... -40C to 125C Junction Temperature ........................................... 150C Storage Temperature Range .................. -65C to 150C Lead Temperature (Soldering, 10 sec) S6 Package ....................................................... 300C
PIN CONFIGURATION
TOP VIEW V+ 1 DIV 2 SET 3 7 6 OUT 5 GND 4 IN IN 1 GND 2 SET 3 TOP VIEW 6 OUT 5 V+ 4 DIV
DCB PACKAGE 6-LEAD (2mm x 3mm) PLASTIC DFN TJMAX = 150C, JA = 64C/W, JC = 10.6C/W EXPOSED PAD (PIN 7) CONNECTED TO GND, PCB CONNECTION OPTIONAL
S6 PACKAGE 6-LEAD PLASTIC TSOT-23 TJMAX = 150C, JA = 192C/W, JC = 51C/W
ORDER INFORMATION
Lead Free Finish
TAPE AND REEL (MINI) LTC6994IDCB-1#TRMPBF TAPE AND REEL LTC6994IDCB-1#TRPBF PART MARKING LFCT LFCT LFCT LFCW LFCW LFCW LTFCV LTFCV LTFCV LTFCX LTFCX LTFCX PACKAGE DESCRIPTION 6-Lead (2mm x 3mm) Plastic DFN 6-Lead (2mm x 3mm) Plastic DFN 6-Lead (2mm x 3mm) Plastic DFN 6-Lead (2mm x 3mm) Plastic DFN 6-Lead (2mm x 3mm) Plastic DFN 6-Lead (2mm x 3mm) Plastic DFN 6-Lead Plastic TSOT-23 6-Lead Plastic TSOT-23 6-Lead Plastic TSOT-23 6-Lead Plastic TSOT-23 6-Lead Plastic TSOT-23 6-Lead Plastic TSOT-23 SPECIFIED TEMPERATURE RANGE 0C to 70C -40C to 85C -40C to 125C 0C to 70C -40C to 85C -40C to 125C 0C to 70C -40C to 85C -40C to 125C 0C to 70C -40C to 85C -40C to 125C LTC6994CDCB-1#TRMPBF LTC6994CDCB-1#TRPBF LTC6994HDCB-1#TRMPBF LTC6994HDCB-1#TRPBF LTC6994CDCB-2#TRMPBF LTC6994CDCB-2#TRPBF LTC6994IDCB-2#TRMPBF LTC6994CS6-1#TRMPBF LTC6994IS6-1#TRMPBF LTC6994HS6-1#TRMPBF LTC6994CS6-2#TRMPBF LTC6994IS6-2#TRMPBF LTC6994HS6-2#TRMPBF LTC6994IDCB-2#TRPBF LTC6994CS6-1#TRPBF LTC6994IS6-1#TRPBF LTC6994HS6-1#TRPBF LTC6994CS6-2#TRPBF LTC6994IS6-2#TRPBF LTC6994HS6-2#TRPBF LTC6994HDCB-2#TRMPBF LTC6994HDCB-2#TRPBF
TRM = 500 pieces. *Temperature grades are identified by a label on the shipping container. Consult LTC Marketing for parts specified with wider operating temperature ranges. Consult LTC Marketing for information on lead based finish parts. For more information on lead free part marking, go to: http://www.linear.com/leadfree/ For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/
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LTC6994-1/LTC6994-2 ELECTRICAL CHARACTERISTICS
SYMBOL tDELAY tDELAY PARAMETER Delay Time Delay Accuracy (Note 4) NDIV 512
l
The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. Test conditions are V+ = 2.25V to 5.5V, IN = 0V, DIVCODE = 0 to 15 (NDIV = 1 to 221), RSET = 50k to 800k, RLOAD = 5k, CLOAD = 5pF unless otherwise noted.
CONDITIONS MIN 1 1.7 2.4
l
TYP
MAX 33.55 2.3 3.0 3.4 4.4 5.1 6.2
UNITS sec % % % % % % %/C %/C % %
8 NDIV 64 NDIV = 1
l
3.8
l l
tDELAY/T
Delay Drift Over Temperature Delay Change With Supply
NDIV 512 NDIV 64 NDIV 512 8 NDIV 64 V+ = 4.5V to 5.5V V+ = 2.25V to 4.5V V+ = 4.5V to 5.5V V+ = 2.7V to 4.5V V+ = 2.25V to 2.7V V+ = 5.5V V+ = 2.25V
0.006 0.008 -0.6 -0.4 -0.9 -0.7 -1.1 -0.2 -0.1 -0.2 -0.2 -0.1 1.0 0.5 0.20 0.05 0.20 0.03 6 * tMASTER 0.4 0.9
l l l l l
% % % %P-P %P-P %P-P %P-P %P-P %P-P s
Delay Jitter (Note 10)
NDIV = 1 NDIV = 8 NDIV = 64 NDIV = 512 NDIV = 4096
tS Power Supply V+ IS(IDLE)
Delay Change Settling Time (Note 9) Operating Supply Voltage Range Power-On Reset Voltage Supply Current (Idle)
tMASTER = tDELAY/NDIV
l l
2.25 165 125 135 105 70 60 65 55 0.97 50 0 1.00 75
5.5 1.95 200 160 175 140 110 95 100 90 1.03 800 V+ 1.5 10
V V A A A A A A A A V V/C k V % nA
RL = , RSET = 50k, NDIV 64 RL = , RSET = 50k, NDIV 512 RL = , RSET = 800k, NDIV 64
V+ = 5.5V V+ = 2.25V V+ = 5.5V V+ = 2.25V V+ = 5.5V V+ = 2.25V
l l l l l l l l
RL = , RSET = 800k, NDIV 512 V+ = 5.5V V+ = 2.25V Analog Inputs VSET VSET/T RSET VDIV VDIV/V+ Voltage at SET Pin VSET Drift Over Temperature Frequency-Setting Resistor DIV Pin Voltage DIV Pin Valid Code Range (Note 5) DIV Pin Input Current Deviation from Ideal VDIV/V+ = (DIVCODE + 0.5)/16
l l l l l l
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LTC6994-1/LTC6994-2 ELECTRICAL CHARACTERISTICS
SYMBOL Digital I/O IN Pin Input Capacitance IN Pin Input Current VIH VIL IOUT(MAX) VOH High Level IN Pin Input Voltage Low Level IN Pin Input Voltage Output Current High Level Output Voltage (Note 7) IN = 0V to V+ (Note 6) (Note 6) V+ = 2.7V to 5.5V V+ = 5.5V V+ = 3.3V V+ = 2.25V VOL Low Level Output Voltage (Note 7) V+ = 5.5V V+ = 3.3V V+ = 2.25V tPD tWIDTH tr tf Propagation Delay V+ = 5.5V V+ = 3.3V V+ = 2.25V V+ = 3.3V V+ = 5.5V V+ = 3.3V V+ = 2.25V V+ = 5.5V V+ = 3.3V V+ = 2.25V IOUT = -1mA IOUT = -16mA IOUT = -1mA IOUT = -10mA IOUT = -1mA IOUT = -8mA IOUT = 1mA IOUT = 16mA IOUT = 1mA IOUT = 10mA IOUT = 1mA IOUT = 8mA
l l l l l l l l l l l l l l
The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. Test conditions are V+ = 2.25V to 5.5V, IN = 0V, DIVCODE = 0 to 15 (NDIV = 1 to 221), RSET = 50k to 800k, RLOAD = , CLOAD = 5pF unless otherwise noted.
PARAMETER CONDITIONS MIN TYP 2.5 10 0.7 * V+ 0.3 * V+ 20 5.45 4.84 3.24 2.75 2.17 1.58 5.48 5.15 3.27 2.99 2.21 1.88 0.02 0.26 0.03 0.22 0.03 0.26 10 14 24 5 1.1 1.7 2.7 1.0 1.6 2.4 0.04 0.54 0.05 0.46 0.07 0.54 MAX UNITS pF nA V V mA V V V V V V V V V V V V ns ns ns ns ns ns ns ns ns ns
Minimum Recognized Input Pulse Width Output Rise Time (Note 8)
Output Fall Time (Note 8)
Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime. Note 2: The LTC6994C is guaranteed functional over the operating temperature range of -40C to 85C. Note 3: The LTC6994C is guaranteed to meet specified performance from 0C to 70C. The LTC6994C is designed, characterized and expected to meet specified performance from -40C to 85C but it is not tested or QA sampled at these temperatures. The LTC6994I is guaranteed to meet specified performance from -40C to 85C. The LTC6994H is guaranteed to meet specified performance from -40C to 125C. Note 4: Delay accuracy is defined as the deviation from the tDELAY equation, assuming RSET is used to program the delay. Note 5: See Operation section, Table 1 and Figure 2 for a full explanation of how the DIV pin voltage selects the value of DIVCODE.
Note 6: The IN pin has hysteresis to accommodate slow rising or falling signals. The threshold voltages are proportional to V+. Typical values can be estimated at any supply voltage using: VIN(RISING) 0.55 * V+ + 185mV and VIN(FALLING) 0.48 * V+ - 155mV Note 7: To conform to the Logic IC Standard, current out of a pin is arbitrarily given a negative value. Note 8: Output rise and fall times are measured between the 10% and the 90% power supply levels with 5pF output load. These specifications are based on characterization. Note 9: Settling time is the amount of time required for the output to settle within 1% of the final delay after a 0.5x or 2x change in ISET . Note 10: Jitter is the ratio of the deviation of the programmed delay to the mean of the delay. This specification is based on characterization and is not 100% tested.
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LTC6994-1/LTC6994-2
V+ = 3.3V, RSET = 200k and TA = 25C unless otherwise noted. Delay Drift vs Temperature (NDIV 64)
1.5 1.0 0.5 DRIFT (%) 0 -0.5 -1.0 -1.5 -50 -25 DRIFT (%) RSET = 50k 3 PARTS 1.5 1.0 0.5 DRIFT (%) 0 -0.5 -1.0 -1.5 -50 -25
TYPICAL PERFORMANCE CHARACTERISTICS
Delay Drift vs Temperature (NDIV 64)
RSET = 200k 3 PARTS 1.5 1.0 0.5 0 -0.5 -1.0 -1.5 -50 -25
Delay Drift vs Temperature (NDIV 64)
RSET = 800k 3 PARTS
50 25 75 0 TEMPERATURE (C)
100
125
50 25 75 0 TEMPERATURE (C)
100
125
50 25 75 0 TEMPERATURE (C)
100
125
699412 G01
699412 G02
699412 G03
Delay Drift vs Temperature (NDIV 512)
1.5 1.0 0.5 DRIFT (%) DRIFT (%) 0 -0.5 -1.0 -1.5 -50 -25 RSET = 50k 3 PARTS 1.5 1.0 0.5 0 -0.5 -1.0
Delay Drift vs Temperature (NDIV 512)
RSET = 200k 3 PARTS 1.5 1.0 0.5 DRIFT (%) 0 -0.5 -1.0
Delay Drift vs Temperature (NDIV 512)
RSET = 800k 3 PARTS
50 25 75 0 TEMPERATURE (C)
100
125
-1.5 -50 -25
50 25 75 0 TEMPERATURE (C)
100
125
-1.5 -50 -25
50 25 75 0 TEMPERATURE (C)
100
125
699412 G04
699412 G05
699412 G06
Delay Drift vs Supply Voltage (NDIV = 1)
1.0 0.8 0.6 0.4 DRIFT (%) DRIFT (%) 0.2 0 -0.2 -0.4 -0.6 -0.8 -1.0 2 RSET = 50k RSET = 200k RSET = 800k 3 4 SUPPLY (V) 5 6
699412 G07
Delay Drift vs Supply Voltage (NDIV = 1)
1.0 0.8 0.6 0.4 0 -0.2 -0.4 -0.6 -0.8 -1.0 2 RSET = 50k RSET = 200k RSET = 800k 3 4 SUPPLY (V) 5 6
699412 G08
Delay Drift vs Supply Voltage (NDIV > 1)
1.0 0.8 0.6 0.4 DRIFT (%) 0.2 0 -0.2 -0.4 -0.6 -0.8 -1.0 2 RSET = 50k, NDIV = 8 RSET = 50k TO 800k, NDIV 512 RSET = 800k, NDIV = 8 3 4 SUPPLY (V) 5 6
699412 G09
RISING EDGE DELAY REFERENCED TO V+ = 4V
FALLING EDGE DELAY REFERENCED TO V+ = 4V
REFERENCED TO V+ = 4V
0.2
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LTC6994-1/LTC6994-2 TYPICAL PERFORMANCE CHARACTERISTICS +
V = 3.3V, RSET = 200k and TA = 25C unless otherwise noted. Delay Error vs RSET (NDIV = 1)
5 4 3 2 ERROR (%) ERROR (%) 1 0 -1 -2 -3 -4 -5 50 100 200 RSET (k ) 400 800
699412 G10
Delay Error vs RSET (8 NDIV 64)
5 4 3 2 ERROR (%) 1 0 -1 -2 -3 -4 -5 50 100 200 RSET (k ) 400 800
699412 G11
Delay Error vs RSET (NDIV 512)
5 4 3 2 1 0 -1 -2 -3 -4 -5 50 100 200 RSET (k ) 400 800
699412 G12
RISING EDGE DELAY 3 PARTS
3 PARTS
3 PARTS
Delay Error vs RSET (NDIV =1)
5 4 3 2 ERROR (%) ERROR (%) 1 0 -1 -2 -3 -4 -5 50 100 200 RSET (k ) 400 800
699412 G13
Delay Error vs DIVCODE
5 4 3 2 ERROR (%) 1 0 -1 -2 -3 -4 -5 0 2 4 6 8 10 DIVCODE 12 14
699412 G14
Delay Error vs DIVCODE
5 4 3 2 1 0 -1 -2 -3 -4 -5 0 2 4 6 8 10 DIVCODE 12 14
699412 G15
FALLING EDGE DELAY 3 PARTS
LTC6994-1 RSET = 50k 3 PARTS
LTC6994-1 RSET = 800k 3 PARTS
RISING EDGE DELAY
FALLING EDGE DELAY
RISING EDGE DELAY
FALLING EDGE DELAY
1.0 0.8 0.6 0.4
VSET Drift vs ISET
1.0 0.8 0.6 0.4 DRIFT (mV)
VSET Drift vs Supply Voltage
1.020 1.015 1.010 1.005 VSET (V) 1.000 0.995 0.990 REFERENCED TO V+ = 4V 2 3 4 SUPPLY (V) 5
699412 G17
VSET vs Temperature
3 PARTS
VSET (mV)
0.2 0 -0.2 -0.4 -0.6 -0.8 -1.0 0 5 REFERENCED TO ISET = 10A 10 ISET (A) 15 20
699412 G16
0.2 0 -0.2 -0.4 -0.6 -0.8 -1.0
0.985 6 0.980 -50 -25 75 0 25 50 TEMPERATURE (C) 100 125
699412 G18
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LTC6994-1/LTC6994-2
V+ = 3.3V, RSET = 200k and TA = 25C unless otherwise noted. Typical VSET Distribution
2 LOTS DFN AND SOT-23 1274 UNITS 300 POWER SUPPLY CURRENT (A) 250 200 150 RSET = 100k, /8, ACTIVE 100 50 0 RSET = 100k, /8, IDLE CLOAD = 5pF RLOAD = 2 3 RSET = 800k, /512 6
699412 G20
TYPICAL PERFORMANCE CHARACTERISTICS
Supply Current vs Supply Voltage
LTC6994-1 IS(ACTIVE) MEASURED WITH fIN = 1/(2 * tDELAY) RSET = 50k, /1, ACTIVE POWER SUPPLY CURRENT (A) 250
Supply Current vs Temperature
LTC6994-1 IS(ACTIVE) MEASURED WITH fIN = 1/(2 * tDELAY) RSET = 50k, /1, ACTIVE 150 RSET = 50k, /1, IDLE RSET = 100k, /8, ACTIVE RSET = 100k, /8, IDLE 50 CLOAD = 5pF RLOAD = -25 RSET = 800k, /512
250
200 NUMBER OF UNITS
200
150
RSET = 50k, /1, IDLE
100
100
50
0 0.98
0.988
0.996 1.004 VSET (V)
1.012
1.02
4 5 SUPPLY VOLTAGE (V)
0 -50
0 25 50 75 TEMPERATURE (C)
100
125
699412 G19
699412 G21
Supply Current vs IN Pin Voltage
250 POWER SUPPLY CURRENT (A) POWER SUPPLY CURRENT (A) 5V IN FALLING 5V IN RISING 250 200
Supply Current vs tDELAY (5V)
POWER SUPPLY CURRENT (A) ACTIVE CURRENT MEASURED USING LTC6994-1 WITH fIN = 1/(2 * tDELAY) /1 /8
250 200
Supply Current vs tDELAY (2.5V)
ACTIVE CURRENT MEASURED USING LTC6994-1 WITH fIN = 1/(2 * tDELAY)
200
150
3.3V IN FALLING
3.3V IN RISING
150
150
/1
/8
100 50 CLOAD = 5pF RLOAD = 0 0.2 0.6 0.4 VIN/V+ (V/V) 0.8 1.0
699412 G22
100 50
100 50
0
0 0.001
V+ = 5V CLOAD = 5pF RLOAD = 0.01 0.1 1 tDELAY (ms)
ACTIVE IDLE 10 100
699412 G23
0 0.001
V+ = 2.5V CLOAD = 5pF RLOAD = 0.01 0.1 1 tDELAY (ms)
ACTIVE IDLE 10 100
699412 G24
IN Threshold Voltage vs Supply Voltage
3.5 3.0 POSITIVE GOING IN PIN VOLTAGE (V) 2.5 JITTER (%P-P) 2.0 1.5 1.0 0.5 0 2 3 4 5 SUPPLY VOLTAGE (V) 6
699412 G25
1.2 1.0 0.8 0.6 0.4
Peak-to-Peak Jitter vs tDELAY
/1, 5.5V PEAK-TO-PEAK tDELAY VARIATION MEASURED OVER 30s INTERVALS 1000
Typical ISET Current Limit vs V+
SET PIN SHORTED TO GND
800
NEGATIVE GOING
/1, 2.25V
ISET (A) /512 /64 0.1 1 tDELAY (ms) /4096 10 100
699412 G26
600
400
/8, 5.5V 0.2 0 0.001 /8, 2.25V 0.01
200
0
2
3
4 5 SUPPLY VOLTAGE (V)
6
699412 G27
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LTC6994-1/LTC6994-2 TYPICAL PERFORMANCE CHARACTERISTICS +
V = 3.3V, RSET = 200k and TA = 25C unless otherwise noted. Input Propagation Delay (tPD) vs Supply Voltage
25 20 RISE/FALL TIME (ns) CLOAD = 5pF 3.0 2.5 OUTPUT RESISTANCE () 2.0 tRISE 1.5 tFALL 1.0 0.5 0
Rise and Fall Time vs Supply Voltage
CLOAD = 5pF 50 45 40 35 30 25 20 15 10 5
Output Resistance vs Supply Voltage
PROPAGATION DELAY (ns)
15 10
OUTPUT SOURCING CURRENT
OUTPUT SINKING CURRENT
5
0
2
3
4 SUPPLY VOLTAGE (V)
5
6
699412 G28
2
3
4 5 SUPPLY VOLTAGE (V)
6
699412 G29
0
2
3
4 5 SUPPLY VOLTAGE (V)
6
699412 G30
Start-Up, RSET = 800k (LTC6994-1)
V+ 2V/DIV IN 2V/DIV OUT 2V/DIV V+ = 2.5V 7.2ms V+ 2V/DIV IN 2V/DIV OUT 2V/DIV
699412 G31
Start-Up, RSET = 50k (LTC6994-2, POL = 1)
500s
1ms/DIV
V+ = 2.5V
100s/DIV
699412 G32
PIN FUNCTIONS
(DCB/S6) + (Pin 1/Pin 5): Supply Voltage (2.25V to 5.5V). This supV
ply should be kept free from noise and ripple. It should be bypassed directly to the GND pin with a 0.1F capacitor.
DIV (Pin 2/Pin 4): Programmable Divider and Polarity Input. The DIV pin voltage (VDIV) is internally converted into a 4-bit result (DIVCODE). VDIV may be generated by a resistor divider between V+ and GND. Use 1% resistors to ensure an accurate result. The DIV pin and resistors should be shielded from the OUT pin or any other traces that have fast edges. Limit the capacitance on the DIV pin to less than 100pF so that VDIV settles quickly. The MSB of DIVCODE (POL) selects the delay functionality. For the LTC6994-1, POL = 0 will delay the rising transition and POL = 1 will delay the falling transition. For the LTC69942, both transitions are delayed so POL = 1 can be used to invert the output.
SET (Pin 3/Pin 3): Delay Setting Input. The voltage on the SET pin (VSET) is regulated to 1V above GND. The amount of current sourced from the SET pin (ISET) programs the master oscillator frequency. The ISET current range is 1.25A to 20A. The delayed output transition will be not occur if ISET drops below approximately 500nA. Once ISET increases above 500nA the delayed edge will transition. A resistor connected between SET and GND is the most accurate way to set the delay. For best performance, use a precision metal or thin film resistor of 0.5% or better tolerance and 50ppm/C or better temperature coefficient. For lower accuracy applications an inexpensive 1% thick film resistor may be used. Limit the capacitance on the SET pin to less than 10pF to minimize jitter and ensure stability. Capacitance less
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LTC6994-1/LTC6994-2 PIN FUNCTIONS
(DCB/S6)
than 100pF maintains the stability of the feedback circuit regulating the VSET voltage.
V+ IN OUT LTC6994 GND V+ C1 0.1F V+
IN (Pin 4/Pin 1): Logic Input. Depending on the version and POL bit setting, rising or falling edges on IN will propagate to OUT after a programmable delay. The LTC6994-1 will delay only the rising or falling edge. The LTC6994-2 will delay both edges. GND (Pin 5/Pin 2): Ground. Tie to a low inductance ground plane for best performance. OUT (Pin 6/Pin 6): Output. The OUT pin swings from GND to V+ with an output resistance of approximately 30. When driving an LED or other low impedance load a series output resistor should be used to limit source/sink current to 20mA.
R1
SET RSET
DIV
699412 PF
R2
BLOCK DIAGRAM (S6 package pin numbers shown)
5 R1 4 R2 V+ DIV 4-BIT A/D CONVERTER DIGITAL FILTER POL
1
IN
INPUT BUFFER EDGECONTROLLED DELAY LOGIC OUTPUT OUT 6 POLARITY (LTC6994-2)
MASTER OSCILLATOR V 1s tMASTER = * SET ISET 50k
MCLK
PROGRAMMABLE DIVIDER /1, 8, 64, 512, 4096, 215, 218, 221
HALT OSCILLATOR IF ISET < 500nA ISET
POR
+ -
VSET = 1V SET 3 ISET RSET 1V
+ -
GND 2
699412 BD
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LTC6994-1/LTC6994-2 OPERATION
The LTC6994 is built around a master oscillator with a 1s minimum period. The oscillator is controlled by the SET pin current (ISET) and voltage (VSET), with a 1s/50k conversion factor that is accurate to 1.7% under typical conditions. 1s VSET tMASTER = * 50k ISET A feedback loop maintains VSET at 1V 30mV, leaving ISET as the primary means of controlling the input-to-output delay. The simplest way to generate ISET is to connect a resistor (RSET) between SET and GND, such that ISET = VSET/RSET . The master oscillator equation reduces to: R tMASTER = 1s * SET 50k From this equation, it is clear that VSET drift will not affect the input-to-output delay when using a single program resistor (RSET). Error sources are limited to RSET tolerance and the inherent accuracy tDELAY of the LTC6994. RSET may range from 50k to 800k (equivalent to ISET between 1.25A and 20A). When the input makes a transition that will be delayed (as determined by the part version and POL bit setting), the master oscillator is enabled to time the delay. When the desired duration is reached, the output is allowed to transition. The LTC6994 also includes a programmable frequency divider which can further divide the frequency by 1, 8, 64, 512, 4096, 215, 218 or 221. This extends the delay duration by those same factors. The divider ratio NDIV is set by a resistor divider attached to the DIV pin. tDELAY = NDIV VSET * * 1s 50k ISET NDIV *RSET * 1s 50k DIVCODE The DIV pin connects to an internal, V+ referenced 4-bit A/D converter that determines the DIVCODE value. DIVCODE programs two settings on the LTC6994: 1. DIVCODE determines the frequency divider setting, NDIV . 2. The DIVCODE MSB is the POL bit, and configures a different polarity setting on the two versions. a. LTC6994-1: POL selects rising or falling-edge delays. POL = 0 will delay rising-edge transitions. POL = 1 will delay falling-edge transitions. b. LTC6994-2: POL selects the output inversion. POL = 1 inverts the output signal. VDIV may be generated by a resistor divider between V+ and GND as shown in Figure 1.
2.25V TO 5.5V V+ LTC6994 DIV R2 GND
699412 F01
R1
Figure 1. Simple Technique for Setting DIVCODE
Table 1 offers recommended 1% resistor values that accurately produce the correct voltage division as well as the corresponding NDIV and POL values for the recommended resistor pairs. Other values may be used as long as: 1. The VDIV/V+ ratio is accurate to 1.5% (including resistor tolerances and temperature effects) 2. The driving impedance (R1||R2) does not exceed 500k.
With RSET in place of VSET/ISET the equation reduces to: tDELAY =
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LTC6994-1/LTC6994-2 OPERATION
If the voltage is generated by other means (i.e., the output of a DAC) it must track the V+ supply voltage. The last column in Table 1 shows the ideal ratio of VDIV to the supply voltage, which can also be calculated as: VDIV V
+
For example, if the supply is 3.3V and the desired DIVCODE is 4, VDIV = 0.281 * 3.3V = 928mV 50mV. Figure 2 illustrates the information in Table 1, showing that NDIV is symmetric around the DIVCODE midpoint.
=
DIVCODE + 0.5 1.5% 16
Table 1. DIVCODE Programming
DIVCODE 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 POL 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 NDIV 1 8 64 512 4,096 32,768 262,144 2,097,152 2,097,152 262,144 32,768 4,096 512 64 8 1 Recommended tDELAY 1s to 16s 8s to 128s 64s to 1.024ms 512s to 8.192ms 4.096ms to 65.54ms 32.77ms to 524.3ms 262.1ms to 4.194sec 2.097sec to 33.55sec 2.097sec to 33.55sec 262.1ms to 4.194sec 32.77ms to 524.3ms 4.096ms to 65.54ms 512s to 8.192ms 64s to 1.024ms 8s to 128s 1s to 16s R1 (k) Open 976 976 1000 1000 1000 1000 1000 887 681 523 392 280 182 102 Short R2 (k) Short 102 182 280 392 523 681 887 1000 1000 1000 1000 1000 976 976 Open VDIV /V+ 0.03125 0.015 0.09375 0.015 0.15625 0.015 0.21875 0.015 0.28125 0.015 0.34375 0.015 0.40625 0.015 0.46875 0.015 0.53125 0.015 0.59375 0.015 0.65625 0.015 0.71875 0.015 0.78125 0.015 0.84375 0.015 0.90625 0.015 0.96875 0.015
POL BIT = 0 10000 1000 100 tDELAY (ms) 10 1 0.1 1 0.01 0.001 0V 0 0.5*V+ INCREASING VDIV 2 3 4 5 6 7 8 9 10
POL BIT = 1
11 12 13 14 15 V+
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Figure 2. Delay Range and POL Bit vs DIVCODE
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11
LTC6994-1/LTC6994-2 OPERATION
Edge-Controlled Delay The LTC6994 is a programmable delay or pulse qualifier. It can perform noise filtering, which distinguishes it from a delay line (which simply delays all input transitions). When the voltage on the LTC6994 input pin (IN) transitions low or high, the LTC6994 can delay the corresponding output transition by any time from 1s to 33.6 seconds. LTC6994-1 Functionality Figures 3 details the basic operation of the LTC6994-1 when configured to delay rising edge transitions (POL = 0). A rising edge on the IN pin initiates the timing. OUT remains low for the duration of tDELAY . If IN stays high then OUT will transition high after this time. If the input doesn't remain high long enough for OUT to transition high then the timing will restart on each successive rising edge. In this way, the LTC6994-1 can serve as a pulse qualifier, filtering out noisy or short signals. On a falling edge at the input, the output will follow immediately (after a short propagation delay tPD).Note that the output pulse width may be extremely short if IN falls immediately after OUT rises. Figure 4 details the operation of the LTC6994-1 when configured to delay falling edges (POL = 1).
tWIDTH IN tPD OUT
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tPD
tPD
tPD
tPD
tPD
tDELAY
tDELAY
tDELAY
Figure 3. Rising-Edge Delayed Timing Diagram (LTC6994-1, POL = 0)
tWIDTH IN tPD OUT
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tPD
tPD
tPD
tPD
tPD
tDELAY
tDELAY
tDELAY
Figure 4. Falling-Edge Delayed Timing Diagram (LTC6994-1, POL = 1)
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12
LTC6994-1/LTC6994-2 OPERATION
LTC6994-2 Functionality Figures 5 details the basic operation of the LTC6994-2 when configured for noninverting operation (POL = 0). As before, a rising edge on the IN pin initiates the timing and, if IN remains high, OUT will transition high after tDELAY . Unlike the LTC6994-1, falling edges are delayed in the same way. When IN transitions low, OUT will follow after tDELAY . If the input doesn't remain high or low long enough for OUT to follow, the timing will restart on the next transition. Also unlike the LTC6994-1, the output pulse width can never be less than tDELAY . Therefore, the LTC6994-2 can generate pulses with a defined minimum width. Figure 6 details the operation of the LTC6994-2 when the output is inverted (POL = 1).
tWIDTH IN tPD OUT tDELAY tDELAY tDELAY tDELAY
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tPD
tPD
tPD
tPD
Figure 5. Both Edges Delayed Timing Diagram (LTC6994-2, POL = 0)
tWIDTH IN tPD OUT tDELAY tDELAY tDELAY tDELAY tPD tPD tPD tPD
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Figure 6. Both Edges Delayed (Inverting) Timing Diagram (LTC6994-2, POL = 1)
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13
LTC6994-1/LTC6994-2 OPERATION
Changing DIVCODE After Start-Up Following start-up, the A/D converter will continue monitoring VDIV for changes. Changes to DIVCODE will be recognized slowly, as the LTC6994 places a priority on eliminating any "wandering" in the DIVCODE. The typical delay depends on the difference between the old and new DIVCODE settings and is proportional to the master oscillator period. tDIVCODE = 16 * (DIVCODE + 6) * tMASTER A change in DIVCODE will not be recognized until it is stable, and will not pass through intermediate codes. A digital filter is used to guarantee the DIVCODE has settled to a new value before making changes to the output. However, if the delay timing is active during the transition, the actual delay can take on a value between the two settings.
DIV 500mV/DIV IN 2V/DIV 4s OUT 2V/DIV LTC6994-1 V+ = 3.3V RSET = 200k 500s/DIV
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Start-Up Time When power is first applied, the power-on reset (POR) circuit will initiate the start-up time, tSTART . The OUT pin is held low during this time and the IN pin has no control over the output. The typical value for tSTART ranges from 0.5ms to 8ms depending on the master oscillator frequency (independent of NDIV): tSTART(TYP) = 500 * tMASTER During start-up, the DIV pin A/D converter must determine the correct DIVCODE before the LTC6994 can respond to an input. The start-up time may increase if the supply or DIV pin voltages are not stable. For this reason, it is recommended to minimize the capacitance on the DIV pin so it will properly track V+. Less than 100pF will not extend the start-up time. At the end of tSTART the DIVCODE and IN pin settings are recognized, and the state of the IN pin is transferred to the output (without additional delay). If IN is high at the end of tSTART, OUT will go high. Otherwise OUT will remain low. The LTC6994-2 with POL = 1 is the exception because it inverts the signal. At this point, the LTC6994 is ready to respond to rising/falling edges on the input.
V+
512s
256s
Figure 7a. DIVCODE Change from 0 to 2
DIV 500mV/DIV IN 2V/DIV 256s OUT 2V/DIV LTC6994-1 V+ = 3.3V RSET = 200k 500s/DIV
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IN 512s tSTART (IN IGNORED) 4s OUT tPD IF IN = 1 AT END OF tSTART* IF IN = 0 AT END OF tSTART* *LTC6994-2 WITH POL = 1 INVERTS THE OUTPUT
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Figure 8. Start-Up Timing Diagram
Figure 7b. DIVCODE Change from 2 to 0
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14
LTC6994-1/LTC6994-2 APPLICATIONS INFORMATION
Basic Operation The simplest and most accurate method to program the LTC6994 is to use a single resistor, RSET , between the SET and GND pins. The design procedure is a 3-step process. Step 1: Select the LTC6994 Version and POL Bit Setting. Choose LTC6994-1 to delay one (rising or falling) input transition. The POL bit then defines which edge is to be delayed. POL = 0 delays rising edges. POL = 1 delays falling edges. Choose LTC6994-2 to delay rising and falling edges. Set POL = 0 for normal operation, or POL = 1 to invert the output. Step 2: Select the NDIV Frequency Divider Value. As explained earlier, the voltage on the DIV pin sets the DIVCODE which determines both the POL bit and the NDIV value. For a given delay time (tDELAY), NDIV should be selected to be within the following range: t tDELAY NDIV DELAY 16s 1s (1) Example: Design a circuit to delay falling edges by tDELAY = 100s with minimum power consumption. Step 1: Select the LTC6994 Version and POL Bit Setting. To delay negative transitions, choose the LTC6994-1 with POL = 1. Step 2: Select the NDIV Frequency Divider Value. Choose an NDIV value that meets the requirements of Equation (1), using tDELAY = 100s: 6.25 NDIV 100 Potential settings for NDIV include 8 and 64. NDIV = 8 is the best choice, as it minimizes supply current by using a large RSET resistor. POL = 1 and NDIV = 8 requires DIVCODE = 14. Using Table 1, choose R1 = 102k and R2 = 976k values to program DIVCODE = 14. Step 3: Select RSET . Calculate the correct value for RSET using Equation (2). RSET = 50k 100s * = 625k 1s 8
To minimize supply current, choose the lowest NDIV value. However, in some cases a higher value for NDIV will provide better accuracy (see Electrical Characteristics). Table 1 can also be used to select the appropriate NDIV values for the desired tDELAY . With POL already chosen, this completes the selection of DIVCODE. Use Table 1 to select the proper resistor divider or VDIV/V+ ratio to apply to the DIV pin. Step 3: Calculate and Select RSET . The final step is to calculate the correct value for RSET using the following equation: RSET = 50k tDELAY * 1s NDIV (2)
Since 625k is not available as a standard 1% resistor, substitute 619k if a -0.97% shift in tDELAY is acceptable. Otherwise, select a parallel or series pair of resistors such as 309k and 316k to attain a more precise resistance. The completed design is shown in Figure 9.
IN OUT LTC6994-1 GND V+ 0.1F SET RSET 625k DIV R1 102k DIVCODE = 14 R2 976k
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2.25V TO 5.5V
Figure 9. 100s Negative-Edge Delay
Select the standard resistor value closest to the calculated value.
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15
LTC6994-1/LTC6994-2 APPLICATIONS INFORMATION
Voltage-Controlled Delay With one additional resistor, the LTC6994 output delay can be manipulated by an external voltage. As shown in Figure 10, voltage VCTRL sources/sinks a current through RMOD to vary the ISET current, which in turn modulates the delay as described in Equation (3): tDELAY = NDIV *RMOD * 50k 1s 1+ RMOD VCTRL - RSET VSET
OUT LTC6994 GND RMOD RSET V+ C1 0.1F V+
Digital Delay Control The control voltage can be generated by a DAC (digital-toanalog converter), resulting in a digitally-controlled delay. Many DACs allow for the use of an external reference. If such a DAC is used to provide the VCTRL voltage, the VSET dependency can be eliminated by buffering VSET and using it as the DAC's reference voltage, as shown in Figure 11. The DAC's output voltage now tracks any VSET variation and eliminates it as an error source. The SET pin cannot be tied directly to the reference input of the DAC because the current drawn by the DAC's REF input would affect the delay. ISET Extremes (Master Oscillator Frequency Extremes)
R1
(3)
IN
VCTRL
SET
DIV R2
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When operating with ISET outside of the recommended 1.25A to 20A range, the master oscillator operates outside of the 62.5kHz to 1MHz range in which it is most accurate. The oscillator will still function with reduced accuracy for ISET < 1.25A. At approximately 500nA, the oscillator will stop. Under this condition, the delay timing can still be initiated, but will not terminate until ISET increases and the master oscillator starts again. At the other extreme, it is not recommended to operate the master oscillator beyond 2MHz because the accuracy of the DIV pin ADC will suffer.
IN V+ OUT LTC6994 0.1F GND V+ C1 0.1F V+
Figure 10. Voltage-Controlled Delay
R1
1/2 LTC6078 0.1F V+
+ -
SET
DIV R2
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DIN P CLK CS/LD
VCC
REF VOUT RMOD
N *R tDELAY = DIV MOD * 50k DIN = 0 TO 4095
1s RMOD DIN 1+ - RSET 4096
LTC1659 GND
RSET
Figure 11. Digitally Controlled Delay
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16
LTC6994-1/LTC6994-2 APPLICATIONS INFORMATION
Settling Time Following a 2x or 0.5x step change in ISET , the output delay takes approximately six master clock cycles (6 * tMASTER) to settle to within 1% of the final value. An example is shown in Figure 12, using the circuit in Figure 10.
VCTRL 2V/DIV IN 5V/DIV OUT 5V/DIV DELAY 2s/DIV LTC6994-1 V+ = 3.3V DIVCODE = 0 RSET = 200k RMOD = 464k tOUT = 3s AND 6s 20s/DIV
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Even an excellent layout will allow some coupling between IN and SET. Additional error is included in the specified accuracy for NDIV = 1 to account for this. Figure 13 shows that /1 supply variation is dependent on coupling from rising or falling inputs. A very poor layout can actually degrade performance further. The PCB layout should avoid routing SET next to IN (or any other fast-edge, wide-swing signal).
1.0 0.8 0.6 0.4 DRIFT (%) 0.2 0 -0.2 -0.4 -0.6 -0.8 -1.0 2 RSET = 50k NDIV = 1 3 4 SUPPLY (V) 5
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FALLING EDGE DELAY
RISING EDGE DELAY
Figure 12. Typical Settling Time
Coupling Error The current sourced by the SET pin is used to bias the internal master oscillator. The LTC6994 responds to changes in ISET almost immediately, which provides excellent settling time. However, this fast response also makes the SET pin sensitive to coupling from digital signals, such as the IN input.
6
Figure 13. Delay Drift vs Supply Voltage
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17
LTC6994-1/LTC6994-2 APPLICATIONS INFORMATION
Power Supply Current The Electrical Characteristics table specifies the supply current while the part is idle (waiting for an input transition). IS(IDLE) varies with the programmed tDELAY and the supply voltage, as described by the equations in Table 2, valid for both the LTC6994-1 and LTC6994-2.
Table 2. Approximate Idle Supply Current Equations
CONDITION NDIV 64
tDELAY
IS(ACTIVE) can be estimated using the equations in Table 3, assuming a periodic input with frequency fIN. The equations assume the input pulse width is greater than tDELAY; otherwise, the output will not transition (and the increase in supply current will be less).
Table 3. Active Increase in Supply Current
CONDITION NDIV 64 NDIV 512 DEVICE LTC6994-1 LTC6994-2 Either Version TYPICAL IS(ACTIVE)* + * (N fIN * V DIV * 5pF + 18pF + CLOAD) + * (N fIN * V DIV * 10pF + 22pF + CLOAD) fIN * V+ * CLOAD
TYPICAL IS(IDLE)
V + * (NDIV * 7pF + 4pF ) V+ + + 2.2 *ISET + 50A 500k
+
*Ignoring resistive loads (assumes RLOAD = )
NDIV 512
V *NDIV * 7pF V + + 1.8 *ISET + 50A 500k tDELAY
+
When an input transition starts the delay timing circuity, the instantaneous supply current increases to IS(ACTIVE). IS(ACTIVE) = IS(IDLE) + IS(ACTIVE)
250 POWER SUPPLY CURRENT (A) V+ = 3.3V INPUT PULSE WIDTH = 1.1 * tDELAY /1, RSET = 50k 150
Figures 14 and 15 show how the supply current increases from IS(IDLE) as the input frequency increases. At higher NDIV settings, the increase in active current is smaller.
250 POWER SUPPLY CURRENT (A)
200 /8, RSET = 50k /1, RSET = 100k /1, RSET = 800k
200
V+ = 3.3V fIN < 1/(2 * tDELAY) TO ALLOW RISING AND FALLING DELAYS TO REACH THE OUTPUT /1, RSET = 50k /8, RSET = 50k
150
100 50 CLOAD = 5pF RLOAD = 0.2
100 50 CLOAD = 5pF RLOAD = 0.1
/1, RSET = 100k /1, RSET = 800k
0 "IDLE"
0.6 0.4 fIN * tDELAY
0.8
1.0
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0 "IDLE"
0.3 0.2 fIN * tDELAY
0.4
0.5
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Figure 14. IS(ACTIVE) vs Input Frequency, LTC6994-1
Figure 15. IS(ACTIVE) vs Input Frequency, LTC6994-2
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18
LTC6994-1/LTC6994-2 APPLICATIONS INFORMATION
Supply Bypassing and PCB Layout Guidelines The LTC6994 is an accurate monostable multivibrator when used in the appropriate manner. The part is simple to use and by following a few rules, the expected performance is easily achieved. Adequate supply bypassing and proper PCB layout are important to ensure this. Figure 16 shows example PCB layouts for both the SOT-23 and DCB packages using 0603 sized passive components. The layouts assume a two layer board with a ground plane layer beneath and around the LTC6994. These layouts are a guide and need not be followed exactly. 1. Connect the bypass capacitor, C1, directly to the V+ and GND pins using a low inductance path. The connection from C1 to the V+ pin is easily done directly on the top layer. For the DCB package, C1's connection to GND is also simply done on the top layer. For the SOT-23, OUT can be routed through the C1 pads to allow a good C1 GND connection. If the PCB design rules do not allow that, C1's GND connection can be accomplished through multiple vias to the ground plane. Multiple vias for both the GND pin connection to the ground plane and the C1 connection to the ground plane are recommended to minimize the inductance. Capacitor C1 should be a 0.1F ceramic capacitor.
IN
2. Place all passive components on the top side of the board. This minimizes trace inductance. 3. Place RSET as close as possible to the SET pin and make a direct, short connection. The SET pin is a current summing node and currents injected into this pin directly modulate the output delay. Having a short connection minimizes the exposure to signal pickup. 4. Connect RSET directly to the GND pin. Using a long path or vias to the ground plane will not have a significant affect on accuracy, but a direct, short connection is recommended and easy to apply. 5. Use a ground trace to shield the SET pin. This provides another layer of protection from radiated signals. 6. Place R1 and R2 close to the DIV pin. A direct, short connection to the DIV pin minimizes the external signal coupling.
OUT LTC6994 V+
GND
C1 0.1F
V+ R1
SET RSET V+ R1 V+ DIV R2 SET RSET C1 OUT GND IN
DIV R2
C1 IN GND SET RSET R2
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V+
OUT V+ DIV R1
DCB PACKAGE
TSOT-23 PACKAGE
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Figure 16. Supply Bypassing and PCB Layout
19
LTC6994-1/LTC6994-2 TYPICAL APPLICATIONS
Delayed One-Shot
IN IN OUT LTC6994-1 GND V+ 0.1F SET 604k DIV 121k SET DIV 392k 5V TRIG OUT
+
DELAYED PULSE OUT 5V 0.1F
LTC6993-1 GND V
1M
tRISE_DELAY = 50ms
tONESHOT = 10ms
IN OUT DELAY 50ms SHOT 10ms
DELAY
SHOT
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Pulse Stretcher
IN IN OUT LTC6994-1 GND V+ 0.1F SET 787k DIV 976k 182k V+ OUT
tMIN = 1ms
OUTPUT PULSE DURATION = tPULSE_IN + 1ms IN
OUT
tMIN
tMIN
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V+
Switch/Relay Debouncer
OR
V+
IN
OUT LTC6994-2 V+
OUT CHATTER V+ 0.1F 1M OR CHATTER STABLE STABLE
GND
SET 154k
DIV 523k
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t = 100ms
OUTPUT GOES TO SAME FINAL LEVEL OF INPUT AFTER STABLE FOR 100ms
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20
LTC6994-1/LTC6994-2 TYPICAL APPLICATIONS
Edge Chatter Filter
IN IN OUT LTC6994-2 GND V+ V+ 0.1F OUT
SET 499k 10s
DIV
INPUT MUST BE STABLE FOR AT LEAST 10s IN
OUT 10s NORMAL 10s 10s NOISY EDGES 10s
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Crossover Gate--Break-Before-Make Interval Timer
V+ LOAD LOW IN LOAD HIGH IN OUT LTC6994-1 GND V+ 0.1F SET 787k DIV V+ 100k VLOAD 442k LOAD FALLING DELAYED 100k P TP0610
IN V+/2
V+ V+ OFF OFF GND 1ms OFF INTERVAL AT EACH TRANSITION OFF
VLOAD
tDELAY = 1ms
100k RISING DELAYED N 2N7000 V+ 0.1F SET 787k DIV 100k
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IN
OUT LTC6994-1 V+
GND
tDELAY = 1ms
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21
LTC6994-1/LTC6994-2 PACKAGE DESCRIPTION
(Reference LTC DWG # 05-08-1715 Rev A)
DCB Package 6-Lead Plastic DFN (2mm x 3mm)
0.70 0.05
3.55 0.05
1.65 0.05 (2 SIDES) PACKAGE OUTLINE
2.15 0.05
0.25 0.05 0.50 BSC 1.35 0.05 (2 SIDES) RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS R = 0.115 TYP R = 0.05 TYP
2.00 0.10 (2 SIDES)
0.40 0.10 4 6
3.00 0.10 (2 SIDES) PIN 1 BAR TOP MARK (SEE NOTE 6)
1.65 0.10 (2 SIDES) PIN 1 NOTCH R0.20 OR 0.25 x 45 CHAMFER 3 1
(DCB6) DFN 0405
0.200 REF
0.75 0.05
0.25 0.05 0.50 BSC
1.35 0.10 (2 SIDES) 0.00 - 0.05 BOTTOM VIEW--EXPOSED PAD
NOTE: 1. DRAWING TO BE MADE A JEDEC PACKAGE OUTLINE M0-229 VARIATION OF (TBD) 2. DRAWING NOT TO SCALE 3. ALL DIMENSIONS ARE IN MILLIMETERS 4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE 5. EXPOSED PAD SHALL BE SOLDER PLATED 6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE TOP AND BOTTOM OF PACKAGE
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22
LTC6994-1/LTC6994-2 PACKAGE DESCRIPTION
(Reference LTC DWG # 05-08-1636)
2.90 BSC (NOTE 4)
S6 Package 6-Lead Plastic TSOT-23
0.62 MAX
0.95 REF
1.22 REF
3.85 MAX 2.62 REF
1.4 MIN
2.80 BSC
1.50 - 1.75 (NOTE 4) PIN ONE ID
RECOMMENDED SOLDER PAD LAYOUT PER IPC CALCULATOR
0.95 BSC 0.80 - 0.90
0.30 - 0.45 6 PLCS (NOTE 3)
0.20 BSC DATUM `A' 1.00 MAX
0.01 - 0.10
0.30 - 0.50 REF
NOTE: 1. DIMENSIONS ARE IN MILLIMETERS 2. DRAWING NOT TO SCALE 3. DIMENSIONS ARE INCLUSIVE OF PLATING 4. DIMENSIONS ARE EXCLUSIVE OF MOLD FLASH AND METAL BURR 5. MOLD FLASH SHALL NOT EXCEED 0.254mm 6. JEDEC PACKAGE REFERENCE IS MO-193
0.09 - 0.20 (NOTE 3)
1.90 BSC
S6 TSOT-23 0302 REV B
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Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
23
LTC6994-1/LTC6994-2 TYPICAL APPLICATION
Press-and-Hold (0.3s to 4s) Delay Timer
V+ ACTIVE HIGH IN 100k OUT LTC6994-1 GND V+ 1M RSET 576k SET DIV 681k tDELAY 3s BOUNCE IN HOLD IN BOUNCE HOLD 0.1F RSET 576k SET DIV 1M tDELAY 3s OUT V
+
V+ 100k ACTIVE LOW IN OUT LTC6994-1 GND V+ 681k 0.1F OUT V+
OUT
DELAY
OUT RSET (k) = 190 * tDELAY (SECONDS)
DELAY
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RELATED PARTS
PART NUMBER LTC1799 LTC6900 LTC6906/LTC6907 LTC6930 LTC6990 LTC6991 LTC6992 LTC6993 DESCRIPTION 1MHz to 33MHz ThinSOT Silicon Oscillator 1MHz to 20MHz ThinSOT Silicon Oscillator 10kHz to 1MHz or 40kHz ThinSOT Silicon Oscillator Fixed Frequency Oscillator, 32.768kHz to 8.192MHz TimerBlox: Voltage-Controlled Silicon Oscillator TimerBlox: Resettable Low Frequency Oscillator TimerBlox: Voltage-Controlled Pulse Width Modulator (PWM) TimerBlox: Monostable Pulse Generator (One-Shot) COMMENTS Wide Frequency Range Low Power, Wide Frequency Range Micropower, ISUPPLY = 35A at 400kHz 0.09% Accuracy, 110s Start-Up Time, 105A at 32kHz Fixed-Frequency or Voltage-Controlled Operation Clock Periods up to 9.5 hours Simple PWM with Wide Frequency Range Resistor-Programmable Pulse Width of 1s to 34s
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24 Linear Technology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408) 432-1900
LT 1010 * PRINTED IN USA
FAX: (408) 434-0507 www.linear.com
LINEAR TECHNOLOGY CORPORA TION 2010

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